Home /UOS — University of Sargodha /Computer Architecture

Computer Architecture BSCS 4 Semester/Term UOS — University of Sargodha 2016

Discussion

Ask a question about this paper, or help someone else with theirs. Answers are emailed to whoever asked.

No questions yet — be the first to ask.

More Computer Architecture papers

See all

Computer Architecture BSCS 2018 UOS University Of Sargodha (UOS) · BSCS Uploaded 3 years ago Download ↓

Computer Architecture BSCS 2016 UOS University Of Sargodha (UOS) · BSCS Uploaded 3 years ago Download ↓

University of Sargodha BS 4** Term Examination 2017. Subject: Computer Science Paper: Computer Architecture (CS:4240) Time Alloweds 2:30 Hours Maximum Marks: 80 (VID University Of Sargodha (UOS) · BSCS Uploaded 3 years ago Download ↓

University of Sargodha BS 4* Term Examination 2017. Subjects Computer Science Paper: Computer Architecture (CS:4240) Time Allowed: 2:30 Hours Maximum Marks: 80 Objective Part University Of Sargodha (UOS) · BSCS Uploaded 3 years ago Download ↓

University of Sargodha BS 6t* Term Examination 2015 Subject: Computer Science Paper: Computer Architecture (CS-420) Time Allowed: 2:30 Hours Maximum Marks: 80 0.1 University Of Sargodha (UOS) · BSCS Uploaded 3 years ago Download ↓

University of Sargodha BS 4** Term Examination 2015 Subject: Computer Science Paper: Computer Architecture (CS-4240) Time Allowed: 2:30 Hours istadni.co Maximum Marks: 80 University Of Sargodha (UOS) · BSCS Uploaded 3 years ago Download ↓

Paper text

University of Sargodha

Department of Computer Science & Information Technology

MID Term Examination 2016

Program: BSCS 4th

Subject: Computer Architecture

Max Marks: 30 marks

Time Allowed: 90 min

Note: All questions are compulsory. Give answers to the point.

Question 1: 10 marks

Consider a memory system that uses a 64-bit address to address at the byte level, plus a

cache that uses a 64-byte line size.

a. Assume a direct mapped cache with a tag field in the address of 40 bits. Show the

address format and determine the following parameters: number of addressable

units, number of blocks in main memory, number of lines in cache, size of tag.

b. Assume an associative cache. Show the address format and determine the

following parameters: number of addressable units, number of blocks in main

memory, number of lines in cache, size of tag.

c. Assume a four-way set-associative cache with a tag field in the address of 9 bits.

Show the address format and determine the following parameters: number of

addressable units, number of blocks in main memory, number of lines in set, number

of sets in cache, number of lines in cache, size of tag.

Question 2: 10 marks

Consider the following pipeline stages to discuss Pipeline hazards in detail.

IF1: The PC calculation and the first stage of the I-cache access

IF2: The second stage of the I-cache access, the branch prediction, the main controller

ID: Instruction decode and forwarding and stall control signal generators

MEM1: The address calculation

MEM2: The D-cache access

EX1: The only execution stage for logic operation and the first stage for adding,

subtracting, and shifting operation

EX2: The second stage for adding, subtracting, and shifting operation

WB: The register write back

Question 3: 5 marks

Briefly explain the branch prediction strategy in the above diagram. Also draw branch history table

that can accommodate this strategy.

[Diagram of branch prediction state machine]

Question 4: 5 marks

Draw diagrams to explain the Michael Flynn characterization of Parallel Computing.