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Digital logic Design AD/BS 1 Semester/Term PU — University of the Punjab 2024

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  • Ayesha Mustafa· 3 days ago

    BS ZOOLOGY first semester Animal diversity ZOOL 101 - university of Punjab 2025

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  • Abubakar· 3 days ago

    Literary criticism

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  • Guest· 4 days ago

    this paper consists of 60 marks but now we have 35 marks paper.

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  • Annie· 5 days ago

    Can you please tell me more past papers please because my exams are starting from next week

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    Did you provide the past papers of the science of society uos?

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Paper text

UNIVERSITY OF THE PUNJAB

AD (2 Years) & BS (4 Years) Degree Program / First Semester - Fall 2024

Paper: Digital Logic Design

Course Code: CC-110

Marks: 60

THE ANSWERS MUST BE ATTEMPTED ON THE ANSWER SHEET PROVIDED

Q.1. Answer the following short questions. (6x5=30)

a) Convert (B9.C)16 to binary number system.

b) Let A = 101001 and B = 101011, perform A-B using 2's complement.

c) Reduce F = (x'y' + z)' + z + xy + wz to three literals using identities and theorems of Boolean algebra.

d) Express F(A,B,C) = A + B'C as sum of minterms, product of sums, and product of maxterms.

e) Prove that (AB' +

C)' = A'C + BC' using truth table.

f) Draw the circuit diagram of a 2-bit magnitude comparator that compares A1A0 and B1B0. The circuit has only one output E, such that E=1, if the inputs are identical.

g) A combinational circuit produces the binary sum of two 2-bit numbers, X1X0 and Y1Y0. The outputs are C, S1, and S0. Provide a truth table of the combinational circuit.

Answer the following questions: (3x10=30)

Question#2:

In a certain chemical processing plant, a liquid chemical is used in a manufacturing process. The chemical is stored in three different tanks. Each tank has a sensor which sends a logic-1 on getting empty otherwise it sends a logic-0. A red LED should turn ON, if any two of the three tanks gets empty. Design a combinational circuit of the chemical processing plant.

Question#3:

What is decoder and multiplexer? Show the constructions of 3x8 decoder using two 2x4 decoders. Implement F (A,B,C) = Σ ( 0, 1, 2, 5,

7) using

i) decoder

ii) 4x1 MUX by keeping A,B as selection inputs of MUX.

Question#4:

Draw the logic circuit diagram of D flip flop. Design a 4-bit register with using D flip flops that operates according to the following function table:

Control Inputs Register

X Y Operation

0 0 No Change

0 1 Parallel Load

1 0 Shift Left

1 1 Shift Right