Digital logic Design ADP/BS University Of Sargodha (UOS) 2025

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ADP/BS 2" Se r (F-24) Examination 2025

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Subject: CS/AT/SE Paper Digital Logic Design (CMPC-5204)

Time Allowed: 02:30 Hours Maximum Marks: 40

Note: Objective part is compulsory. Attempt any three questions from subjective part.

(Hlustrate your answer with diagram where needed).

Objective Part \ (Compulsory)

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Q.1. Write short answers of the following in 2-3 lines €ach on your answer sheet. (2*8)

i. Represent the decimal number 6,248 in BCD.

il. Find the complement of the functions.F = x(¥Z + yz).

iii. Demonstrate the validity of the following identities by means of truth tables: DeMorgan’s theorem

for three variables: (X+Y+Z)=(XYZ

iv. Why we use K-Map?

v. What is Multiplexer?

vi. What is Complements theorem?

vii. Define don’t-care conditions.

viii. What is a carry propagate adder? |

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University of Sargodha #

ADP/BS 27 Semester (24) Examination 2025

Subject: CS/AT/SE paper: Digital Logic Design (CMPC-5204)

ubject:

i Marks: 40

Time Allowed: 02:30 Hours Maximum Marks

(Ilustrate your answer with diagram where needed),

SN

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ii. Find the complement of the functions.F = x(¥Z + yz).

for three variables: (X+Y+7Z)= (XYZ)

iv. Why we use K-Map? h

viii. What is a carry propagate adder?

| Part (8*3)

Q.2. Draw logic diagram of four-to-one-line m Itipléxer.

Q.3. Draw the circuit diagram of half adder and full adder. Draw truth table of half adder. Also write

Boolean expression of half adder only. Show how a full adder can be converted to a full subtracter?

Q.4. Draw seven segment logic diagram and its truth table.

Q.5. Simplify the following Boolean functions, using Karnaugh maps

F(4,B,C,D)=% (4,6, 7,15).

Q.6. Draw the following circuit with NANDs and NORs only.

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