Digital logic Design BS/MPhil Information Technology/MS Information Technology 2 Semester/Term University Of Sargodha (UOS) 2021

University of Sargodha

BS 2nd Semester/Term. Exam 2021

Subject: Information Technology

Paper: Digital Logic and Design (ITSC:192)

Time Allowed: 02:30 Hours

Maximum Marks: 60

Note: Objective part is compulsory. Attempt any three questions from subjective part.

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Objective Part

(Compulsory)

Q.1. Write short answers of the following in 2-3 lines each on your answer sheet

What are literals?

ii.

Write dual of 0 • 1 = 1 • 0-0

• Define null clement theorem

What are decoders?

What are priority circuits?

Vi.

ViV

vhi.

ix. 1

x.

Xi.

What are arithmetic circuits?

What is a propagation delay?

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What is minimum number of bits that can be added using a fuli adder?

What are synchronous sequential circuits?

A flip-flop copies input to output on which edge of the clock?

A divide-by-N counter has how many outputs?

xii~ What is a synchronizer?

(2*12)

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Q.2.

Subjective Part

(3*12)

Simplity the following Boolean equations using Boolean theorems. Check for correctness using a truth

table or K-map.

R.3.

2.4.

Y= ABCD+ABC+ ABCD+ ABD+7 BCD+ BCD+ A

Draw a 4:1 multiplexer with minimum number of gates.

Following table shows the truth table for a Boolean function Y. Using De Morgan's Theorem, derive

the product-of-sums canonical form of Y from the sum-of-products form of complement of Y.

A

0

1

0

0

1

0

0

1

0

1

1

0

1

1

1

• M

1

0

1

0

2.5. Given the following iogic circuit, draw an equivalent logic circuit with max-terms.

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Find the propagation delay and contamination delay of the circuit shown in the following eircuit.

According to his data book, each gate has a propagation delay of 80 picoseconds (ps) and a

contamination delay of 50 ps.

D, -

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