University of Sargodha BS 2 Term Examination 2017 Subject: Computer Science/Software Fngineering Paper: Digital Logic Design (CMP:2210) Time Allowed: 2:30 Hours Maximum Marks: 80
Discussion
Ask a question about this paper, or help someone else with theirs. Answers are emailed to whoever asked.
No questions yet — be the first to ask.
More Digital logic Design papers
See all
Digital Logic and Design University of Sargodha BS 2nd Term Examination 2024
Uploaded 10 months ago
Download ↓
BSIT-CS-Digital Logic Design University Of Sargodha UOS 2023.
Uploaded 1 year ago
Download ↓
BSIT- CS Digital Logic Design UOS 2022
Uploaded 1 year ago
Download ↓
BSIT-Digital Logic Design University Of Sargodha 2021.
Uploaded 1 year ago
Download ↓
BSIT-Digital Logic Design (page 2) University Of Sargodha UOS 2020.
Uploaded 1 year ago
Download ↓
BSIT-Digital Logic Design (page 1) University Of Sargodha UOS 2020.
Uploaded 1 year ago
Download ↓
Paper text
University of Sargodha
BS 2 Term Examination 2017
Subject: Computer Science/Software Fngineering
Paper: Digital Logic Design (CMP:2210)
Time Allowed: 2:30 Hours
Maximum Marks: 80
Note: Objective part is compulsory. Attempt any three questions from subjective part.
Objective Part (Compulsory)
Q.1.
Write short answers of the following in 2-3 lines each.
(16*2)
Convert into equivalent binary number (1AF) 16
ii:
Write BCD equivalent of Excess-3.
illS Express -99 as an 8-bit number in the sign-magnitude, 2's complement form.
Add the following BCD numbers: 10LF0210 + 10011101
V:
vi:
vii!
vili:
ix:
X.
Xi:
xii.
xili.
Using Boolean algehra techniques, sir plity this expression A B - A: (+ O, A (8 +C)
State Demorgan's law to verify that negative-OR gate is equivalent to NAND gate.
Prove that A + A-B = A + B
Draw the gate implementation of the function: A + B•C + A-B-C
Minimize the following SOP using; K-Map: A-B•C +Ã-B-Č + A-B-C + A• B•C + A•B-C
Determine the logic required to derode (1011)2 by producing a HIGH on the output.
Draw diagram of SR-Latch using NA ND-gates.
Explain how an Exclusive-NOR gate is used to compare to binary bits.
What is difference between Serial in/ Parallel out registers and Parallel in /Parallel out
registers?
xiv.®
XV.
XVi:
What is latch? Draw logic circuit for SR latch.
What is difference between A syrichronous counter and Synchronous counter?
Draw the logic diagram of XO'R gate using all NAND-gates.
Subjective Part
(3*16)
Q.2.
Q.3.
What are counters? Draw BCD ap/down counter using synchronous counter.
Convert the following Boolean expression into Standard SOP:
B • C+ A•B + A•B•C + A-B-C-D + A-B-C-D + A•B•C-D
Map the standard SOP on a K-map simplify and implement it using logic diagram.
0.4.
UStDifferentiate between Look ahead Carry Adders and Ripple carry.
0.5.
Suppose you are working as a lead engineer in Ferrari Corporation it is observed that in hilly
areas Ferrari is experiences fatal accidents due to break failure of all four wheels. You are
requested to design a simple and cost effective safety strategy to overcome and reduce
chances of accidents.
It is an advice given by your higher management that if two or more than two breaks of
wheels fail an alarm must be triggered for the driver. This alarm will help driver to reduce
speed or visit works hop for maintenance.
Q.6.
Implement an Edge. Triggered T flip flop. Describe its functioning and draw truth table.
visit website: ustadni.com